Because the maximum ready latency on the Avalon-ST interface is 8, you can only set this register to a maximum value of The transmitter control discards any new data in the FIFO buffer until the end of frame is reached. By default, the width of all statistics counters are 32 bits. The IP core meets all functional and timing requirements for the device family. On the receive path, connect the clock provided by the PHY device 2. Full and half-duplex only. Transmit data write enable.

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By default, this bit is set to 0. Bit 0 of word offset 0x12 is always set to 0, thus any value written to it is ignored.

[PATCH] Altera TSE: ALTERA_TSE should depend on HAS_DMA

Asserted by the PCS function to indicate that a collision was detected during frame transmission. All signals on the Avalon-ST receive interface are synchronized on the rising edge of this clock.

Set this clock to the required frequency to get the desired bandwidth on the Avalon-ST transmit interface.

A value of 1 indicates that the link partner has received 3 consecutive matching ability values from the device. The comma detection function restarts the search for a valid comma character if the receive synchronization state machine loses the link synchronization. This parameter is disabled if you do not turn on Enable timestamping.


Use the depth of your FIFO buffer to determine this threshold. Hash-code mode selection for multicast address resolution. RGMII in gigabit mode.

Always set bit 0 linkx 1 and bits1—9 to 0. Registers to configure the IEEE v2 feature. Tie this clock low if you are not using an external reconfiguration controller. Intel uses the following definitions for the transmit and receive latencies for the PCS function with an embedded PMA: Typical value is The number of valid broadcast frames received. Required offset location of checksum correction.

Linux-Kernel Archive: [PATCH] Altera TSE: ALTERA_TSE should depend on HAS_DMA

Each section corresponds to a page in the Parameter Settings tab in the parameter editor interface. The auto-negotiation process is completed. Intel used a highly parameterizeable transaction-based testbench to test the following aspects of the IP core: This count includes both good and errored frames.

Set the signal to a value less than or equal to MHz. Variable-length section-full threshold of the receive FIFO buffer. Transmit start of packet. The number of valid and erroneous broadcast frames transmitted, as well as broadcast frames transmitted during late and excessive collision occasions. A direct connection to an optical module is provided through an external SFP optical module. A correctable error occurred and the error has been corrected at the output.


Triple-Speed Ethernet Intel FPGA IP User Guide

The MAC function can accept frames with the following address types: Data bit data written to or read from the PHY device. To read the counter, read the lower 32 bits first, then followed by the extended statistic counter bits.

The backoff period is generated from a pseudo-random process, truncated binary exponential backoff. Collision occurs only in a half-duplex network. The Altefa function always accepts broadcast frames. This threshold can serve as a warning about potential FIFO buffer congestion. MAC control frame enable on receive.

Lniux state machine increments an internal error counter for each invalid character received and incorrectly positioned comma character.